1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to transistors having enhanced performance by using a silicon/germanium (Si/Ge) in the drain/source regions to enhance charge carrier mobility in the channel region of the transistor.
2. Description of the Related Art
The fabrication of integrated circuits requires the formation of a large number of circuit elements, wherein the field effect transistor may represent an important component in advanced logic circuit designs. Generally, a plurality of process technologies are currently practiced for forming field effect transistors, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently the most promising approach due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the overall conductivity of the channel region substantially determines the performance of the MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The continuing shrinkage of the transistor dimensions, however, entails a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. For example, with a reduced channel length, the control of the channel region may become increasingly difficult, which is also referred to as short channel effect. Hence, various design measures, such as sophisticated dopant profiles, increased capacitive coupling of the gate electrode to the channel region and the like, have been developed, some of which may, however, negatively affect the charge carrier mobility in the channel region or may otherwise compromise the transistors. In view of this situation and since the continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, necessitates the adaptation of existing complex processes and possibly the new development of highly complex process techniques, it has been proposed to also enhance the channel conductivity of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length, thereby achieving a performance improvement that is comparable with the advance to a future technology node while avoiding or at least postponing many of the above process adaptations associated with device scaling.
One efficient mechanism for increasing the charge carrier mobility is the modification of the lattice structure in the channel region, for instance by creating tensile or compressive stress so as to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively. For example, creating uniaxial tensile strain in the channel region along the channel increases the mobility of electrons, which, in turn, may directly translate into a corresponding increase in the conductivity of N-channel transistors. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. The introduction of stress or strain engineering in the fabrication process of integrated circuits is an extremely promising approach, since, for example, strained silicon may be considered as a “new” type of semiconductor material, which may enable the fabrication of fast powerful semiconductor devices without requiring new expensive semiconductor materials and manufacturing techniques adapted to these new materials.
An efficient mechanism for enhancing the hole mobility of PMOS transistors may be implemented by forming a strained silicon/germanium alloy in the drain and source regions of the P-channel transistors, wherein the compressively strained drain and source regions create uniaxial strain in the adjacent silicon channel region. To this end, the drain and source regions of the PMOS transistors are selectively recessed, while the NMOS transistors are masked and subsequently the silicon/germanium layer is selectively formed in the PMOS transistor by epitaxial growth. Although this technique offers significant advantages in view of performance gain of the PMOS transistor and thus of the entire CMOS device, if an appropriate design is used that balances the performance gain of the PMOS transistor, a performance gain less than expected may be obtained in advanced applications, when higher germanium concentrations are used to further enhance the strain level in the channel region and thus increasing the hole mobility.
Generally, a higher germanium concentration of the silicon/germanium alloy may result in a more pronounced lattice mismatch between the strain-inducing alloy and the silicon template material, which is considered advantageous for further increasing the hole mobility in the corresponding drain and/or source regions of P-channel transistors. It turns out, however, that an increased germanium concentration may result in a more pronounced interaction of the silicon/germanium alloy with materials and processes that are to be applied during the further processing of the semiconductor device. For example, the chemical reaction and thus modification of the silicon/germanium alloy with respect to a plurality of processes, such as cleaning processes, oxidation processes, etch processes and the like, may be higher compared to substantially pure silicon material, thereby contributing to additional material loss, which may finally result in a less pronounced gain in performance. Additionally, the increased degree of material loss of the silicon/germanium alloy compared to the drain and source regions of N-channel transistors may also result in a loss of dopant species, thereby increasing the series resistance of the corresponding drain and source areas in the P-channel transistor. For this reason, in some conventional approaches, a very pronounced overfill during the selective epitaxial growth process may be applied in order to compensate for the increased material loss during the further processing, which may, however, lead to a negative effect, such as pronounced surface topography, increased transistor variability, reduced throughput in the epitaxial growth process and the like.
Moreover, upon increasing the germanium concentration, which may be considered appropriate for enhancing hole mobility, as discussed above, a desired reduction of the overall resistance of the drain/source path in P-channel transistors may be less pronounced or may even be overcompensated for by process irregularities during the formation of a metal silicide in the drain and source regions. It is well known that metal silicide, such as cobalt silicide, nickel silicide, nickel/platinum silicide and the like, may have a significantly lower resistivity compared to even highly doped silicon material. For this reason, the overall series resistance in sophisticated P-channel transistors may be significantly reduced by providing the metal silicide regions, which may also represent contact areas for contact elements that may be formed in a contact structure that encloses and passivates the transistor elements. During the metal silicide formation, after cleaning and thus preparing exposed semiconductor surface areas for the subsequent manufacturing sequence, a layer of refractory metal is deposited and subsequently annealed in order to initiate a chemical reaction between the refractory metal and the silicon species in the drain and source regions. Thereafter, non-reacted metal may be removed on the basis of well-established selective wet chemical etch recipes. Thereafter, if required, additional treatments such as heat treatments may be performed in order to obtain a stable form of the metal silicide, which may have a desired low resistance state. During the subsequent processing, an interlayer dielectric material is deposited, for instance in the form of silicon nitride and silicon dioxide, which is then patterned to receive contact openings, wherein the associated etch process may finally stop on and in the metal silicide regions. Consequently, the characteristics of the metal silicide may represent an important aspect with respect to the overall performance of the transistor elements since the metal silicide significantly determines the overall series resistance and also acts as an etch stop material during the complex patterning process for forming the contact openings.
It has been observed that an increased germanium concentration in the drain and source regions of P-channel transistors may have a significant influence on the characteristics of the metal silicide material, which may result in a reduced stability, which in turn may result in a reduced conductivity and a modified etch behavior. Consequently, a gain in performance of sophisticated P-channel transistors may be difficult to be achieved on the basis of increasing the germanium concentration, even if a significant overfill during the selective epitaxial growth process may be applied, due to the inferior characteristics of the resulting metal silicide regions, as explained above.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.